ARM EN0-001 Actual Free Exam Questions & Community Discussion

Exam Code/Number: EN0-001
Exam Name/Title: ARM Accredited engineer
Certification Provider: ARM
Corresponding Certification: ARM Certification

Exam Questions: 210
Updated On: Jun 25, 2026

Question #1

Which THREE of the following items should be preserved by software when entering dormant mode? (Choose three)

A. Contents of the Level 1 data cache

B. The CP15 Multiprocessor Affinity Register

C. All User mode general-purpose registers

D. Contents of the Level 2 data cache

E. The Floating Point Status and Control Register (FPSCR)

F. Current Program Status Register (CPSR)

Discussion 0

Correct Answer: C,E,F Vote an answer

Question #2

In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)

A. VA! = PA; No address translations; instructions may be cached but not data

B. VA == PA; Address translations take place; data may be cached but not instructions

C. VA == PA; No address translations; instructions may be cached but not data

D. VA == PA; No address translations; instructions and data are not cached

Discussion 0

Correct Answer: C Vote an answer

Question #3

A re-entrant interrupt handler would typically be used to:

A. Allow an interrupt handler to be relocated in memory

B. Allow an external interrupt to interrupt an SVC handler

C. Avoid the need for an interrupt handler to use a stack.

D. Reduce response time for higher priority interrupts

Discussion 0

Correct Answer: D Vote an answer

Question #4

What is the maximum value of the immediate field in an ARM SVC instruction?

A. 0xF

B. 0xFFFFFF

C. 0x0

D. 0xFF

Discussion 0

Correct Answer: B Vote an answer

Question #5

According to the AAPCS, how many bytes are used to store a C variable of type 'int' in memory?

A. 4 bytes

B. 2 bytes

C. 8 bytes

D. 1 byte

Discussion 0

Correct Answer: A Vote an answer

Question #6

Which of the following is a REQUIRED feature in the ARMv7 architecture?

A. The Thumb-2 instruction set

B. Integer division instructions

C. A memory management unit

D. NEON

Discussion 0

Correct Answer: A Vote an answer

Question #7

When developing a product using the standard ARM C library, what is the minimum effort required to re-target all platform-specific functions in the library?

A. Locate the stack in an area of RAM

B. Set the locale variable appropriately

C. All functions in the standard library must be rewritten

D. Replace all functions which use semi-hosting

Discussion 0

Correct Answer: D Vote an answer

Question #8

In a system using the Security Extensions, how does the Secure Monitor execute a switch from Secure to Non-secure state?

A. Sets the NS bit in SCTLR and performs an exception return - all registers are banked in hardware and switched automatically

B. Saves Secure register contents, sets all registers to zero, sets the NS bit in SCTLR and branches directly to Normal world code

C. Encrypts Secure register contents, sets the NS bit in SCTLR and branches directly to Normal world code

D. Saves Secure register contents, loads Non-secure ones from memory, sets the NS bit in SCTLR and performs an exception return

Discussion 0

Correct Answer: D Vote an answer

Question #9

A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?

A. Instruction cache invalidate only

B. Data cache clean and instruction cache invalidate

C. Data cache invalidate and instruction cache invalidate

D. Instruction cache clean only

Discussion 0

Correct Answer: B Vote an answer

Question #10

Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?

A. Use of the divide-by 64 counting option to avoid an overflow of the cycle counter

B. A dedicated real-time clock to provide the total cycle count

C. Modification of the application software being profiled, to insert timestamps at regular intervals

D. Use of the overflow interrupts, to extend the range of the built-in 32-bit counter

Discussion 0

Correct Answer: D Vote an answer

Question #11

In a Cortex-A processor, assume an initial value of R1 =0x80004000.
If the following instruction causes a data abort, what value will R1 contain on entry to the abort handler?
LDR R0, [R1, #8]!

A. R1 contents are unpredictable

B. 0x80004000

C. 0x80004008

D. 0x80003FF8

Discussion 0

Correct Answer: B Vote an answer

Question #12

Which is the best power saving mode to use while waiting to obtain a lock on a semaphore?

A. Standby

B. Deep sleep

C. Shutdown

D. Dormant

Discussion 0

Correct Answer: A Vote an answer

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