ARM EN0-001 Actual Free Exam Questions & Community Discussion
The automatic removal of a cache line from a cache to free the location is known as cache line:
Correct Answer: A
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In an ARMv7-A processor, with which level of the memory system is the Memory Management Unit (MMU) associated?
Correct Answer: B
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In an ARMv7-A processor, which control register is used to enable the Memory Management Unit (MMU)?
Correct Answer: C
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Which privileged mode can kernel code use to get direct access to the User mode registers R13 and R14?
Correct Answer: C
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Assume a little-endian system.
What is the value of R5 after the execution of the following piece of code?
What is the value of R5 after the execution of the following piece of code?
Correct Answer: C
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Which one of these statements is TRUE about code running on final hardware without a debugger attached?
Correct Answer: C
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In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?
Correct Answer: A
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In which of the following scenarios would cache maintenance operations be necessary in an ARMv7 system?
Correct Answer: A
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Literal pool loads to access constants at run-time can be minimized by:
Correct Answer: B
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In an experiment, the time taken for an application to complete a given task is measured using a stopwatch. Which THREE of the following make up the total time? (Choose three)
Correct Answer: A,C,D
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An Advanced SIMD intrinsic has the prototype:
int16x4_t vmul_n_s16(int16x4_t a, int16_t b);
How many multiplications does this intrinsic compute?
int16x4_t vmul_n_s16(int16x4_t a, int16_t b);
How many multiplications does this intrinsic compute?
Correct Answer: B
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If a Generic Interrupt Controller (GIC) implements 64 priority levels, which priority field bits hold the priority value?
Correct Answer: D
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