ARM EN0-001 Actual Free Exam Questions & Community Discussion

  • Exam Code/Number: EN0-001
  • Exam Name/Title: ARM Accredited engineer
  • Certification Provider: ARM
  • Corresponding Certification: ARM Certification
  • Exam Questions: 210
  • Updated On: Jun 25, 2026
In general, when programming in C, stack accesses will be reduced by:
Correct Answer: A Vote an answer
In Thumb state an ARMv7-A processor can execute:
Correct Answer: C Vote an answer
Implementing loops using a decrementing counter which exits the loop when a counter reaches zero can be beneficial for power and performance. This is because:
Correct Answer: C Vote an answer
Which instruction would be used to return from a Reset exception?
Correct Answer: D Vote an answer
In Architecture ARMv7-A which one of the following has a known physical address at power-on reset?
Correct Answer: A Vote an answer
Which of the following operations would count as intrusive to normal processor operation?
Correct Answer: D Vote an answer
Processors which implement the ARMv7-A architecture can be configured to allow unaligned memory access. Unaligned accesses have a number of advantages, disadvantages, and limitations.
Which TWO of the following statements are true? (Choose two)
Correct Answer: B,D Vote an answer
Which of the following is an external exception?
Correct Answer: B Vote an answer
A deeply embedded real-time industrial control system is missing some hard real-time interrupt deadlines. Which of the following performance analysis techniques is the most suitable for identifying which routines are causing the problem?
Correct Answer: C Vote an answer
In a Cortex-A processor, after which TWO of these events is a cache maintenance operation required to ensure reliable code execution? (Choose two)
Correct Answer: A,E Vote an answer
A 32KB 4-way set associative instruction cache supports a cache line size of 64 bytes. How many bits are required to index a cache line in a way?
Correct Answer: A Vote an answer
Which power mode describes the state where the ARM processor is powered down, but its Level 1 caches remain powered?
Correct Answer: A Vote an answer
0
0
0
10