ARM EN0-001 Actual Free Exam Questions & Community Discussion
Under which of the following circumstances is TLB maintenance always required?
Correct Answer: A
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The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?
Correct Answer: D
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Within the ARMv7 architecture, which one of the following features is unique to the ARMv7-A profile?
Correct Answer: D
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What view in a debugger displays the order in which functions were called?
Correct Answer: D
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Which one of the following statements best describes the function of vector catch logic?
Correct Answer: A
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Which of the following ARM processors has a superscalar micro architecture?
Correct Answer: B
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When using the default ARM tool-chain libraries for bare-metal applications. I/O functionality is rerouted and handled by a connected debugger. This is often referred to as semihosting. Which one of the following explanations BEST describes how this feature can be implemented by a debugger?
Correct Answer: C
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Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.
How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?
How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?
Correct Answer: A
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The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?
Correct Answer: B
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How many bytes of stack are needed to pass parameters when calling the following function?
int foo( short arg_a, long long arg_b, char arg_c, int arg_d )
int foo( short arg_a, long long arg_b, char arg_c, int arg_d )
Correct Answer: D
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An ARM processor connected to a Generic Interrupt Controller (GIC) is handling an active interrupt 11. A new interrupt 12 that is received at the GIC is forwarded to the processor, and the active interrupt 11 is preempted. Which of the following possible values of 11's priority (P1), 12's priority (P2) and the processor's priority mask (PM) permit this to happen? Assume there are 256 priority levels implemented.
Correct Answer: B
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